#ifndef _SEC_PCI_H_
#define _SEC_PCI_H_

#define  PCI_CLASS_BRIDGE           0x06
#define  PCI_CLASS_SHIFT            24
#define  PCI_SUBCLASS_BRIDGE_HOST   0x00
#define  PCI_SUBCLASS_SHIFT         16

#define  PCI_COMMAND_IO_ENABLE      0x00000001
#define  PCI_COMMAND_MEM_ENABLE     0x00000002
#define  PCI_COMMAND_MASTER_ENABLE  0x00000004

#define  PCI_STATUS_PERR_CLR        0x80000000
#define  PCI_STATUS_SERR_CLR        0x40000000
#define  PCI_STATUS_MABORT_CLR      0x20000000
#define  PCI_STATUS_MTABORT_CLR     0x10000000
#define  PCI_STATUS_TABORT_CLR      0x08000000
#define  PCI_STATUS_MPERR_CLR       0x01000000
#define  PCI_STATUS_PERRRESPEN      0x00000040

  
#endif /* _SEC_PCI_H_ */
